Method and apparatus for providing timing analysis for packet streams over packet carriers

ABSTRACT

A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).

FIELD

The exemplary embodiment(s) of the present invention relates tocommunications network. More specifically, the exemplary embodiment(s)of the present invention relates to timing analysis relating to packetstreams.

BACKGROUND

A network environment typically includes various network devices, suchas routers, line modules, hubs, and/or switches, for delivery of digitalinformation via conventional network transporting formats such aspackets and frames. Packets, packet frames, data streams, and/or datatraffics typically travel from source devices to destination devices viaone or more packet switched networks (“PSNs”) or networks. Informationpertaining to the transfer of data packet(s) and/or frame(s) through thenetwork(s) is usually embedded within the packet and/or frame itself.Each packet, for instance, traveling through multiple nodes via one ormore communications networks such as Internet and/or Ethernet, cantypically be handled independently from other packets in a packet streamor traffic. Each node which may include routing, switching, and/orbridging engines processes incoming packets or frames, and determineswhere the packet(s) or frame(s) should be forwarded.

To deliver high performance, it is critical for a network or PSN tomaintain high speed data traffic flowing through circuit emulationservice (“CES”) circuits with minimal packet loss and/or drop. CES, forexample, allows packet transport via synchronous circuits such as T1/E1over asynchronous networks. Note that T1 is a digital carrier signalthat transmits digital signal with a data rate of about 1.544 megabitsper second. T1, for example, contains twenty four digital channels andrequires a network device having digital connection(s). E1, which issimilar to T1, is used for digital transmission with a data rate ofabout 2.048 megabits per second. Unlike T1, E1 has 32 channels at thespeed of 64 Kbps per channel.

A CES carrier typically does not know the content of data stream thatthe carrier transports, as well as timing characteristics associatedwith the data stream. However, when a timing problem occurs at theendpoint of a CES, it is usually difficult to debug because withoutinvasive debugging techniques, it is often hard to ascertain the root ofthe problem. Such invasive procedure(s) can render outage(s) of networkservice to all connected customers, invasive procedure(s) typically isthe last option to debug the problems. For example, when a legacytime-division multiplexing (“TDM”) circuit is replaced with a SAToP(Structure-Agnostic TDM over Packet) or CESoPSN (circuit emulationservice over PSN) link(s), TDM data streams generated at one endpoint ofSAToP can fail due to unpredictable reasons, such as incorrect deviceconfiguration, network congestion, circuit overloading, and the like.Note that incorrect or inaccurate timing configuration at one endpointcircuit could cause the other far-end circuit to fail.

SUMMARY

One embodiment of the present invention discloses a timing analyzer in anetwork device able to provide timing analysis over one or more networkcircuits. The timing analyzer, in one aspect, receives a data packettraveling across a circuit emulation service (“CES”) circuit such as T1or E1 circuit. Upon obtaining an arrival timestamp associated with thedata packet, the arrival timestamp is stored in a timestamp buffer inaccordance with a first-in first-out (“FIFO”) storage sequence. Afteridentifying the oldest arrival timestamp in the timestamp buffer, anoffset is generated based on the result of comparison between thearrival timestamp and the oldest timestamp. The timing analyzer can alsobe configured to generate timing reports on-demand based on generatedoffset(s).

Additional features and benefits of the exemplary embodiment(s) of thepresent invention will become apparent from the detailed description,figures and claims set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

The exemplary embodiment(s) of the present invention will be understoodmore fully from the detailed description given below and from theaccompanying drawings of various embodiments of the invention, which,however, should not be taken to limit the invention to the specificembodiments, but are for explanation and understanding only.

FIG. 1 is a block diagram illustrating a network configuration using atiming analyzer configured to improve network performance in accordancewith one embodiment of the present invention;

FIG. 2 is a block diagram illustrating a network device having aningress element, egress element, and timing analyzer in accordance withone embodiment of the present invention;

FIG. 3 is a flowchart illustrating a process able to identify timingoffsets in accordance with one embodiment of the present invention;

FIG. 4 is a flowchart illustrating a process capable of identifyingtiming wandering over a period of time in accordance with one embodimentof the present invention;

FIG. 5 is a logic block diagram illustrating timing analyzer using atimestamp buffer in accordance with one embodiment of the presentinvention; and

FIG. 6 is a flowchart illustrating a process of timing analyzer using atimestamp buffer in accordance with one embodiment of the presentinvention.

DETAILED DESCRIPTION

Exemplary embodiment(s) of the present invention is described herein inthe context of a method, device, and apparatus for enhancing overallnetwork performance by providing timing analysis to packets travelingthrough T1 or E1 carriers.

Those of ordinary skills in the art will realize that the followingdetailed description of the exemplary embodiment(s) is illustrative onlyand is not intended to be in any way limiting. Other embodiments willreadily suggest themselves to such skilled persons having the benefit ofthis disclosure. Reference will now be made in detail to implementationsof the exemplary embodiment(s) as illustrated in the accompanyingdrawings. The same reference indicators will be used throughout thedrawings and the following detailed description to refer to the same orlike parts.

In the interest of clarity, not all of the routine features of theimplementations described herein are shown and described. It will, ofcourse, be understood that in the development of any such actualimplementation, numerous implementation-specific decisions may be madein order to achieve the developer's specific goals, such as compliancewith application- and business-related constraints, and that thesespecific goals will vary from one implementation to another and from onedeveloper to another. Moreover, it will be understood that such adevelopment effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking of engineering for those ofordinary skills in the art having the benefit of embodiment(s) of thisdisclosure.

Various embodiments of the present invention illustrated in the drawingsmay not be drawn to scale. Rather, the dimensions of the variousfeatures may be expanded or reduced for clarity. In addition, some ofthe drawings may be simplified for clarity. Thus, the drawings may notdepict all of the components of a given apparatus (e.g., device) ormethod.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skills in the art to which the exemplary embodiment(s)belongs. It will be further understood that terms, such as those definedin commonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand this exemplary embodiment(s) of the disclosure.

The term “system” or “device” is used generically herein to describe anynumber of components, elements, sub-systems, devices, packet switchelements, packet switches, access switches, routers, networks, computerand/or communication devices or mechanisms, or combinations ofcomponents thereof. The term “computer” includes a processor, memory,and buses capable of executing instruction wherein the computer refersto one or a cluster of computers, personal computers, workstations,mainframes, or combinations of computers thereof.

IP communication network, IP network, or communication network means anytype of network having an access network that is able to transmit datain a form of packets or cells, such as ATM (Asynchronous Transfer Mode)type, on a transport medium, for example, the TCP/IP or UDP/IP type. ATMcells are the result of decomposition (or segmentation) of packets ofdata, IP type, and those packets (here IP packets) comprise an IPheader, a header specific to the transport medium (for example UDP orTCP) and payload data. The IP network may also include a satellitenetwork, a DVB-RCS (Digital Video Broadcasting-Return Channel System)network, providing Internet access via satellite, or an SDMB (SatelliteDigital Multimedia Broadcast) network, a terrestrial network, a cable(xDSL) network or a mobile or cellular network (GPRS/EDGE, or UMTS(where applicable of the MBMS (Multimedia Broadcast/Multicast Services)type, or the evolution of the UMTS known as LTE (Long Term Evolution),or DVB-H (Digital Video Broadcasting-Handhelds)), or a hybrid (satelliteand terrestrial) network.

Embodiment(s) of the present invention discloses a timing analyzercapable of providing timing analysis over one or more network circuits.The timing analyzer, in one aspect, is configured to receive a datapacket traveling across a circuit emulation service (“CES”) circuit suchas T1 or E1 circuit. After generating an arrival timestamp associatedwith the data packet, the arrival timestamp is stored in a timestampbuffer based on a first-in first-out (“FIFO”) storage sequence. Forexample, the timestamp buffer can be a FIFO shift register. Afterretrieving the oldest arrival timestamp within the timestamp buffer, anoffset is generated or calculated by comparing between the arrivaltimestamp and the oldest timestamp. A timing report, which can bedemanded in real time, can be generated based on the offset. In oneaspect, an alarm is raised if the offset falls outside of a predefinedrange of limits.

FIG. 1 is a block diagram 100 illustrating a network configuration usinga timing analyzer configured to improve network performance inaccordance with one embodiment of the present invention. Diagram 100, inone embodiment, includes a PSN, MPLS network 102 (or cloud), two nodes104-106, and two regional networks 156-158. Interfaces 108-110 can beEthernet interfaces that are used to bridge and/or transfer data packetsand/or frames between nodes 104 and 106 via PSN 102. It should be notedthat the underlying concept of the exemplary embodiment(s) of thepresent invention would not change if one or more blocks (or elements orconnections) were added to or removed from diagram 100.

PSN or MPLS 102, which may be situated between Data Link Layer andNetwork Layer, is a global based communications network capable ofproviding data transfer between circuit-based systems (or clients) andpacket-based systems (or clients). PSN or MPLS 102, hereinafter referredto as PSN 102, is able to handle various types of data format, such asIP, ATM, SDH, SONET, TDM, and/or Ethernet data streams. Note that theconcept of embodiment(s) of the network configuration would not alter ifPSN 102 is replaced with another types of global communicationsnetwork(s), such as Wide Area Network(s) (“WAN”), Internet, MetroEthernet Network (“MEN”), Metropolitan Area Network (“MAN”), and thelike.

A CES circuit network is a regional and/or private network system sinceCES links are used to dedicate CES services to a group of knowncustomers. CES networks 156-158, for example, are circuit-basedswitching networks, usually based on SONET/PDH/SDH technologies.Frame-based CES networking technologies are also capable of transmittingmultiple signals simultaneously over a single transmission path using,for instance, an interleaving time-slot mechanism. The interleavingtiming-slot mechanism, for example, packs multiple data streams witheach stream having a speed of 64 kilobits per second (“Kbps”) perchannel such as a T1 channel. Note that T1 has a capacity of 1.544 Mbpsand E1 has a capacity of 2.048 Mbps. It should be note that CES networks156-158 may include other networks, such as MEN, MAN, WAN, and/or acombination of MEN, MAN, LAN, and/or WAN.

To transport CES data packets/frames through a PSN such as Internet, CESprovides TDM services to customers (or providers) by emulating TDMcircuits over a PSN. TDM services include Plesiochronous DigitalHierarchy (“PDH”), Synchronous Optical Network (“SONET”), and/orSynchronous Digital Hierarchy (“SDH”) services. PDH includes T1 and E1lines while SONET/SDH includes STS-1, STS-3, et cetera.

A CES circuit, for example, is a point-to-point link and facilitates adata flow between a circuit-switching network and a packet-switchingnetwork. To transfer multiple bit streams simultaneously over multiplesub-channels, a time domain, for example, is divided into multiple timeslots wherein each time slot is designated to transport one bit stream.With implementation of Ethernet CES, CES technologies are migrating tothe world of packet network(s).

Referring back to FIG. 1, node 104 is a network device capable ofreceiving data from a circuit 152 (or CES) and routing data onto acircuit 150. Node 104, which can be a router, a switch, a bridge, or acombination of router, switch, and/or bridge, includes a timing analyzer160, an egress element 122 and an ingress element 120 wherein elements120-122 are coupled to network 156 and PSN 102. Ingress element 120 iscapable of receiving CES data stream or frames with a reference clock140 over connection 112. Reference clock 140 provides a clock frequencyused to clock data onto a bus or connection 112. After receipt of CESdata stream, ingress element 120 (CES→PSN IWF) forwards or routesreceived data stream(s) to its destination via a CES circuit 150 throughPSN 102. Egress element 122, on the other hand, receives CES data streamor packets via a CES circuit 152 through PSN 102. Egress element 122, inone embodiment, includes a clock domain management capable ofcharacterizing and/or recovering reference clock from a data streamreceived. The data stream is subsequently forwarded by egress element122 to its destination using recovered clock frequency 146 viaconnection 118. It should be noted that node 104 may include additionalingress and/or egress element(s).

Similarly, node 106 is a network device capable of receiving data from acircuit 150 (or CES) and routing data onto a circuit 152. As node 104,node 106 can be a router, a switch, a bridge, or a combination ofrouter, switch, and/or bridge. Node 106 includes a timing analyzer 162,an egress element 132 and an ingress element 130 wherein elements130-132 are coupled to network 158 and PSN 102. Ingress element 130receives CES data stream or data frames having a reference clock 142 viaconnection 114. Reference clock 142 provides a clock frequency used toclock data onto a bus or connection 114. After receipt of CES datastream, ingress element 130 performs CES→PSN IWF and forwards the datastream to its destination via CES circuit 152 across PSN 102. Egresselement 132, on the other hand, receives the CES data stream via CEScircuit 150 across PSN 102. Egress element 132, in one embodiment,includes a clock domain management capable of characterizing and/orrecovering reference clock from the received data stream. The datastream is forwarded by egress element 132 to its destination usingrecovered clock frequency 144 over connection 116. It should be notedthat node 106 can include additional ingress and/or egress element(s).

Egress element 122 or 132 includes PSN and CES interworking functionincluding adaptive clock recovery feature(s). The PSN and CESinterworking function, in one embodiment, includes a clock domainmanagement capable of selecting or recovering a clock frequency used toclock data stream onto a bus or connection 118. The clock domainmanagement uses usage rate of a traffic buffer such as a jitter bufferto recover the reference clock. Ingress element 120 or 130, on the otherhand, includes CES and PSN interworking function(s) capable of receivingdata frames over bus 112 or 114 clocked by reference clock frequency 140or 142, respectively.

Timing analyzer 160 or 162 is used to analyze timing characteristics ofdata packet(s) traveling through a PSN. Timing analyzer 160, forexample, is able to inform user or carrier that certain circuits havefailed or is about to fail because of timing offsets or timing wanderover a period of time. An advantage of using timing analyzer 160 or 162is that it allows a user or vendor to correct potential timing relatedproblem(s) in accordance with timing offsets before the network fails.

FIG. 2 is a block diagram 200 illustrating a network device having aningress element, egress element, and timing analyzer in accordance withone embodiment of the present invention. Diagram 200 includes PSN 202,jitter buffer 204, timestamp buffer 206, ingress element 208, controller210, egress element 212, timing analyzer 220, and offset component 216.Block 218, in one example, indicates output of TDM streams or packetstimed at an output rate or egress rate. Ingress element 208, in oneembodiment, includes at least a portion of timing analyzer 220. Itshould be noted that the underlying concept of the exemplaryembodiment(s) of the present invention would not change if one or moreblocks (or elements or connections) were added to or removed fromdiagram 200.

Timing analyzer 220, which can be a hardware, software, firmware, orcombination of hardware, software, and firmware components, includestimestamp buffer 206, portion of ingress element 208, and portion ofoffset component 216. Timestamp buffer 206 is a storage buffer able tostore timestamps relating to packets arrival times. For example, iftimestamp buffer 206 has 16,384 entries of storage space for storing16,384 timestamps, timestamp buffer 206 is capable of holding 16,384timestamps wherein the oldest timestamp is the arrival time of a packetthat is received 16,384 packets ago. Timestamp buffer 206, in oneembodiment, is a FIFO shift register or a circular buffer capable ofstoring a predefined number of timestamps (i.e., 16,384 of timestamps)which are used to determine deviation of packet arrival rate from PSN202. It should be noted that the 16,384 entries in timestamp buffer 206is an arbitrary number, and it can be adjusted based on theapplications.

Deviation of packet arrival rate, in one aspect, is represented byoffsets. The offsets are calculated by stored timestamps versus currenttimestamps. Depending on the applications, deviation can indicatepotential problems or timing related errors within the network. Notethat a portion of timestamps or offsets may be used to determine ratechange or time adjustment over a period of time when packets arereconstructed into TDM data for transmission.

Jitter buffer 204, which is a temporary storage device or shiftregister, is able to accumulate a predetermined number of packets orSAToP packets. The stored packets are queued in jitter buffer 204according to sequence numbers of the queued packets before they arebeing routed. The predetermined number of SAToP packets that can bestored in jitter buffer 204 is selected in such a way that jitter buffer204 will not be empty due to certain predefined network conditions. Forexample, a predefined network condition may be selected in response toreducing certain network impairments such as jitter and/or wander. Itshould be noted that CES includes a number of variants, such as SAToPand CESoPSN.

Ingress rate calculation block 230 of ingress element 208, in oneembodiment, includes a monitor component, stamp generator, offsetcalculator, and timing comparator. While the monitor component monitorsincoming packets or SAToP packets from PSN 202, the stamp generatorgenerates a timestamp each time a packet or SAToP packet arrives fromPSN 202. After logging a newly generated timestamp in one of 16,384entries of timestamp buffer 206, the offset calculator calculates timedifference between the arrival time of the most recent packet and thearrival time of the oldest packet indicated by timestamp buffer 206. Inone example, the offset calculator is able to generate an offset basedon PPM by comparing between the most recent arrival time of a packet andthe arrival time of a packet arrived 16,348 packets ago. The timingcomparator provides a deviation or divergence value from the result ofcomparison between the offset and an ideal time range (or a range ofacceptable limits).

Note that the ideal time for a TDM frequency can be 1,544,000 bits persecond over a T1 carrier. Alternatively, the ideal time for a TDMfrequency can be 2,048,000 bits per second over an E1 carrier. A rangeof acceptable limits, in one embodiment, can be plus (+) or minus (−) 25PPM. For instance, if the deviation value is less than +/−25 PPM, thecurrent timing is basically acceptable and timing adjustments are notneeded. If the deviation value, however, is greater than +/−25 PPM, thecurrent timing may need to be adjusted depending on the applications.Note that the range of +/−25 PPM is an exemplary range, and the rangecan change based on the applications.

In one embodiment, timing analyzer 220 is configured to facilitatetiming reconstruction of a TDM stream based on the arrival rate ofpackets. Egress rate calculation block 232, which can be part of egresselement 212, is able to clock outbound SAToP packet as it is sent forreconstruction into TDM data. Block 232 is also capable of calculatingtime difference between the most recently generated timestamp and atimestamp stored in midway in the circular buffer (i.e., 8,174 packetsago).

Adaptive rate control mechanism 236 takes rate calculations from block232 and block 230 to generate an outbound rate for sending TDM datastream. It should be noted that adjusting egress rate should occurslowly over time as oppose to the changing rate of ingress rate whichcan occur more rapidly. Slow changing over egress rate, in one example,prevents transient conditions on PSN 202 from being reflected in theegress data clock rate.

Offset component 216, in one embodiment, is an offset processing modulewhich is configured to activate a set of predefined actions based on theresult of comparison between the offset and the range of acceptablelimits. For example, offset component 216 may raise an alarm if theoffset falls outside of the range of acceptable limits. Also, a log oflock rate may be entered in a local memory or record when the offsetfall within the range of limits. Moreover, offset component 216 may senda warning message to a service provider or customer indicating certaindevice(s) may be incorrectly configured, congested, overloading, or thelike. Also, offset component 216 can be configured to assist adaptiverate control mechanism 236 to adjust egress clock rate for outgoing TDMstreams.

During an operation, upon receipt of a packet A or SAToP packet A fromPSN 202, ingress rate calculation block 230 generates a timestamp Awhich is associated with arrival time of the packet A. As the packet Areaches to jitter buffer 204 for queuing, block 230 retrieves the oldesttimestamp stored in timestamp buffer 206 and compares the oldesttimestamp with timestamp A. Note that if timestamp buffer 206 has 16,384entries and it is full, the oldest timestamp indicates the arrival timeassociated with a packet that is 16,384 packets ago. An offset iscalculated based on the oldest timestamp and timestamp A. Based on theresult of offset in view of a predefined range of limits, offsetcomponent 216 takes a set of predefined actions which will reduceoverall device or system failure(s).

An advantage of using timing analyzer 220 in a router is that it is ableto facilitate timing reconstruction of TDM stream based on the arrivalrate of packets across PSN 202. For instance, a router takes a packet orpackets as they arrive and store them in jitter buffer 204. Afterrecording timestamps associated with packets as they arrive, the routermeasures the stored timestamps over time and calculates offsets based onarrival times of packets. For example, a PSN may transmit one (1) packetper one (1) millisecond (“ms”) or packets arrive one (1) ms apart. If,for instance, packets arrive a little faster from PSN side, the TDMstream should also leave a little faster on the TDM side. Similarly, ifpackets arrive a little slower, the outbound TDM steam should also begated a little slower. Although the operating frequency at source nodeacross PSN is unknown, the router reconstructs the egress rate on theTDM side in accordance with the speed of arriving packets on the PSNside.

Timing analyzer 220, in one embodiment, provides non-invasive diagnosticinformation to identify issue(s) or potential failure(s) quickly withoutthe use of third-party test equipments and/or intrusive diagnosismethods. For example, a router, able to provide SAToP data stream viaPSN 202, employs various hardware such as chips and/or chipsets capableof running CES or SAToP protocol. The router using a set of timingtables and timing algorithm is able to reconstruct timing of the T1 orE1 signal traveling over its pathways. For example, the microcode andits supervisory code can calculate the timing for T1 or E1 circuit. Anapplication code of router compares the offset to a set ofuser-definable criteria and raises an alarm when any of the circuitsfall outside of the desirable range limits. It should be noted that areport or status relating to recorded offsets can be generatedon-demand.

Another advantage of employing timing analyzer 220 is that it providesan automated way to analyze timing characteristics of T1 or E1 circuitstraveling over SAToP or CESoPSN. In yet another benefit of using timinganalyzer is that it removes the need for external equipment to analyzethe timing.

FIG. 3 is a flowchart 300 illustrating a process able to identify timingoffsets in accordance with one embodiment of the present invention.Flowchart 300 illustrates thresholds that can be checked instantaneouslyand do not require stored PPM data. At block 302, the process checks tosee if the ingress PPM is outside some predefined range. If the ingressPPM is within the predefined range or limits, the process indicates thatthe ingress rate is similar to the expected T1 or E1 nominal rate. Forexample, the ingress PPM is not to exceed +/−5 PPM of T1 nominal rate orpredefined limits. If, however, the ingress PPM exceeds the predefinedrange of limits (or some other predefined customer value), the processproceeds to block 304. At block 304, the process logs an anomaly statusin a log or record, and raises an alarm to warn administrator(s) aboutpotential error or failure.

At block 306, the process examines whether the egress rate has convergedin view of ingress rate. Note that under the normal operation, theegress rate should converge to meet the ingress rate at a predefinedtime period. If the egress rate has converged, the process proceeds toblock 308. For instance, the egress rate has converged if egress rate iswithin 1 to 5 PPM of ingress rate. At block 308, the process notes theconvergence in a log to indicate a rate lock. Otherwise, the processlogs the instances where the rate did not converge in a timely manner.Alternatively, the process may also record duration for rate to reachthe rate lock.

During initial establishment of a SAToP connection, various datastructures and state machines are initialized to determine an egressrate or outbound speed for packets to be sent. Upon rate calculationbased on packets collected over a period of time, an ingress rate can bequickly determined according to the rate at which packets arrive fromthe PSN side. The egress rate, however, is generally adjusted slowlyover time to match the ingress rate. In other words, once the system isstable and if network conditions remain stable, neither egress rate noringress rate should fluctuate widely over time until device and/orcircuit(s) failure occurs.

FIG. 4 is a flowchart 400 illustrating a process capable of identifyingtiming wandering over a period of time in accordance with one embodimentof the present invention. Flowchart 400 is based on thresholds thatcannot be checked until measurements are collected and offsets arecalculated. At block 402, the process checks to see where the wanderwhich is indicated by PPM exceeds a predefined wander threshold. Notethat the wander threshold is for the T1 or E1 signal. If the offsetwhich may be indicated by PPM does not exceed the wander threshold, theprocess proceeds to the next block. Otherwise, the process proceeds toblock 404. At block 404, after analyzing a portion or window of a seriesof packets collected, a peak-to-peak range of PPM is measured. If themeasurement is greater than expected limits such as +5 PPM, an anomalyis logged and an alarm is subsequently raised.

At block 406, the process checks to see whether the change of ingressrate is greater than the thresholds. If the change is greater than thethresholds, the process, at block 408, predicts that according to recentarrival rate jump, a device change or failure may have occurred. Theprocess notes the change in ingress rate and records lost rate lock in alog when a rate change or jump is detected.

At block 410, the process exams to see whether egress rate has divergedover time. If the divergence is true which means that the egress ratehas changed unexpectedly regardless of the ingress rate, the processproceeds to block 412. It should be noted that if the PPM calculatedexceeds the threshold, an alarm, for example, is raised. At block 412,the process may predict certain internal error(s) or potentialfailure(s) in the router itself. The anomaly is subsequently noted inthe log. It should be noted that if PPMs are off too much, an alarm isset off. Note that PPM of offset falls outside of threshold may indicatedevice failing, inaccurate device configuration, bad circuit connection,congestion, damages, loading, and the like.

FIG. 5 is a logic block diagram 500 illustrating timing analyzer using atimestamp buffer 510 within a router in accordance with one embodimentof the present invention. Diagram 500 includes a T1 (or E1) circuit 502,packet 504, timestamp 506, clock 508, timestamp buffer 510, and a rangeof limits 518. Note the T1 circuit 502 can be a CES or SAToP capable oftransmitting data. It should be noted that the underlying concept of theexemplary embodiment(s) of the present invention would not change if oneor more blocks (or elements or connections) were added to or removedfrom diagram 500.

When the router or network device receives packet 504 transmitted acrossT1 carrier 502 from a PSN, the timing analyzer stamps or generates atimestamp 506 in accordance with a local clock 508. After storingtimestamp 506 at the top of timestamp buffer 510, the timing analyzerretrieves oldest timestamp 516 from the bottom of the stack or buffer510. Oldest timestamp 516 is the oldest timestamp in timestamp buffer510 such as the timestamp for a packet that is 16,384 packets ago. Block520 compares timestamps 506 and 516 and generates an offset based on theresult of the comparison. The offset, in one embodiment, is representedby PPM. Block 522 compares the offset with a range of limits 518 whichis a set of predefined limitations. The result of the comparison isstored in a log 530. If the result indicates that the offset fallsoutside of the range of limits 518, an alarm is raised and broadcastedvia gate logic 524. Block 532, coupled to log 530, is capable ofgenerating a report on-demand based on the information in log 530.

The exemplary aspect of the present invention includes variousprocessing steps, which will be described below. The steps of the aspectmay be embodied in machine or computer executable instructions. Theinstructions can be used to cause a general purpose or special purposesystem, which is programmed with the instructions, to perform the stepsof the exemplary aspect of the present invention. Alternatively, thesteps of the exemplary aspect of the present invention may be performedby specific hardware components that contain hard-wired logic forperforming the steps, or by any combination of programmed computercomponents and custom hardware components.

FIG. 6 is a flowchart 600 illustrating a process of timing analyzerusing a timestamp buffer in accordance with one embodiment of thepresent invention. At block 602, a process capable of generating timingoffsets associated with a network circuit receives a first data packettraveling across a first CES circuit. For example, the first data packetis received from a T1 carrier which is configured to support SAToP orCESoPSN circuit. Alternatively, the first data packet travels across anE1 carrier via a first CES circuit.

At block 604, a first arrival timestamp or first timestamp associatedwith the first data packet is obtained. For example, a timestamp isgenerated at the time when the first data packet is received at the portof the network device. Alternatively, the process is able to extract anembedded timestamp from the first data packet if the packet contains itsown timestamp.

At block 606, the first arrival timestamp is stored in a first timestampbuffer based on a FIFO storage sequence. In one embodiment, the firstarrival timestamp is stored in a circular buffer containing a predefinednumber of entries for storing timestamps. For example, the process isable to identify one of 16,384 storage entries as the next storage entryfor storing the first arrival timestamp. The FIFO storage sequenceallows a packet arrival time to be temporary saved in the buffer fortime duration of the next 16,384 packets. When the 16,385 packet isreceived, the oldest timestamp is discarded or shifted out of queue tomake room for the new arrival. Note that the total storage capacity of atimestamp buffer can change based on the applications.

At block 608, the oldest arrival timestamp in the first timestamp bufferis identified. In other words, the process is able to retrieve theearliest stored content from the first timestamp buffer. In one aspect,the first timestamp buffer is a shift register, and the earliest storedcontent in the first timestamp buffer will be shifted out as soon as thenew timestamp arrives.

At block 610, a first offset is generated by comparing between the firstarrival timestamp and the oldest timestamp. In one example, the processgenerates PPM data to represent the first offset based on the result ofcomparison between the first arrival timestamp and the oldest timestamp.In one embodiment, the implementation of comparison or calculation willnot start until the timestamp buffer is filled.

At block 612, upon demand by a user, an on-demand report is produced inresponse to the first offset. In addition, the process is capable ofsetting or raising an alert when the first offset is greater than apredefined PPM limits. Note that the predefined PPM can have a rangebetween +25 PPM and −25 PPM. For example, a warning message is sent whenthe first offset falls outside of a predefined range. Alternatively,rate lock status is recorded in a log when the first offset falls withina predefined range. The process is further capable of receiving a seconddata packet traveling across a first CES circuit. Upon obtaining asecond arrival timestamp associated with the second data packet, thesecond arrival timestamp is stored in the first timestamp buffer basedon a FIFO storage sequence. In one embodiment, the process is capable ofreceiving a third data packet traveling across a second CES circuit.Upon obtaining a third arrival timestamp associated with the third datapacket, the third arrival timestamp is stored in a second timestampbuffer based on a FIFO storage sequence. After identifying an oldestarrival timestamp in the second timestamp buffer in accordance with theFIFO storage sequence, a third offset is generated by comparing betweenthe third arrival timestamp and the oldest arrival timestamp of thesecond timestamp buffer. A second timing report can also be generated inresponse to the third offset.

While particular embodiments of the present invention have been shownand described, it will be obvious to those of skills in the art thatbased upon the teachings herein, changes and modifications may be madewithout departing from this exemplary embodiment(s) of the presentinvention and its broader aspects. Therefore, the appended claims areintended to encompass within their scope all such changes andmodifications as are within the true spirit and scope of this exemplaryembodiment(s) of the present invention.

What is claimed is:
 1. A method for generating timing offsets associatedwith a network circuit, comprising: receiving a first data packettraveling across a first circuit emulation service (“CES”) circuit;obtaining a first arrival timestamp associated with the first datapacket; storing the first arrival timestamp in a first timestamp bufferbased on a first-in first-out (“FIFO”) storage sequence; identifying anoldest arrival timestamp in the first timestamp buffer in accordancewith the FIFO storage sequence; generating a first offset by comparingbetween the first arrival timestamp and the oldest arrival timestamp;generating a timing report in response to the first offset; andrecording rate lock status in a log when the first offset falls within apredefined range.
 2. The method of claim 1, further comprising sending awarning message when the first offset falls outside of a predefinedrange.
 3. The method of claim 1, wherein receiving a first data packettraveling across the first CES circuit includes receiving a bit streamtransported by a T1 carrier.
 4. The method of claim 1, wherein receivinga first data packet traveling across the first CES circuit includesreceiving a bit stream transported by an E1 carrier.
 5. The method ofclaim 1, wherein obtaining the first arrival timestamp associated withthe first data packet includes generating a timestamp at a time when thefirst data packet is received at a port of a network device.
 6. Themethod of claim 1, wherein storing the first arrival timestamp in thefirst timestamp buffer includes storing the first arrival timestamp in acircular buffer containing a predefined number of entries for storingtimestamps.
 7. The method of claim 6, wherein storing the first arrivaltimestamp in the circular buffer containing a predefined number ofentries for storing timestamps includes identifying one storage entry inthe circular buffer for storing the first arrival timestamp.
 8. Themethod of claim 1, wherein identifying an oldest arrival timestamp inthe first timestamp buffer in accordance with the FIFO storage sequenceincludes retrieving earliest stored content from the first timestampbuffer.
 9. The method of claim 1, wherein generating the first offset bycomparing between the first arrival timestamp and the oldest timestampincludes generating parts per million (“PPM”) data representing thefirst offset in response to comparison between the first arrivaltimestamp and the oldest timestamp.
 10. The method of claim 9, whereingenerating the timing report in response to the first offset includessetting an alert when the first offset is greater than a predefined PPM.11. The method of claim 1, further comprising: receiving a second datapacket traveling across the first CES circuit; obtaining a secondarrival timestamp associated with the second data packet; and storingthe second arrival timestamp in the first timestamp buffer based on aFIFO storage sequence.
 12. The method of claim 11, further comprising:receiving a third data packet traveling across a second CES circuit;obtaining a third arrival timestamp associated with the third datapacket; storing the third arrival timestamp in a second timestamp bufferbased on a FIFO storage sequence; identifying an oldest arrivaltimestamp in the second timestamp buffer in accordance with the FIFOstorage sequence; generating a third offset by comparing between thethird arrival timestamp and the oldest arrival timestamp of the secondtimestamp buffer; and generating a second timing report in response tothe third offset.
 13. A method for providing timing analysis of anetwork circuit, comprising: generating, by a packet switching device, aplurality of arrival timestamps in accordance with a plurality of datapackets traveling across a circuit emulation service (“CES”) circuit;calculating a set of offsets representing in parts per million (“PPM”)data in response to comparison between the plurality of arrivaltimestamps and prior stored arrival timestamps in a first-in first-outbuffer; obtaining a predefined wander threshold associated with the CEScircuit; recording an anomaly in a log and raising an alarm when any ofthe set of offsets exceeds the predefined wander threshold; identifyinga change of ingress rate in response to the set of offsets; comparingthe change of ingress rate with the predefined wander threshold; andlogging lost rate lock when the change of ingress rate is greater thanthe predefined wander threshold.
 14. The method of claim 13, furthercomprising: identifying a change of egress rate in response to the setof offsets; comparing the change of egress rate with the predefinedwander threshold; and logging a second anomaly in the log when thechange of egress rate is greater than the predefined wander threshold.15. The method of claim 13, further comprising: generating a timinganalysis status report based on the log; and forwarding the timinganalysis status report to user on-demand.
 16. A network device,configured to generate timing offsets associated with a network circuit,comprising: an ingress component coupled to a first circuit emulationservice (“CES”) circuit and configured to generate a first timestampindicating arrival time of a first data packet traveling across thefirst CES circuit; a first timestamp buffer coupled to the ingresscomponent and configured to store a plurality of arrival timestampsbased on a first-in first-out (“FIFO”) storage sequence; a ratecalculator coupled to the first timestamp buffer and configured tocompare an oldest timestamp in the first timestamp buffer with newlyarrived timestamp to identify an offset; an ingress rate manager coupledto the rate calculator and configured to generate a timing report inresponse to the offset; and a log coupled to the ingress rate managerand configured to record rate lock status when the first offset fallswithin a predefined range.
 17. The network device of claim 16, whereinthe ingress component is coupled to a second CES circuit and configuredto generate a second timestamp indicating arrival time of a second datapacket traveling across the second CES circuit.
 18. The network deviceof claim 17, further comprising a second timestamp buffer coupled to theingress component and configured to store the second timestamp based ona circular storage sequence.